1. Field of the Invention
The present invention relates to a DC offset cancellation circuit and more particularly, to a DC offset cancellation circuit for a discrete time receiver capable of minutely adjusting a DC offset and extending a DC offset adjustment range.
2. Description of the Related Art
Because a discrete time filter involves the occurrence of an LO (Local Oscillator) leakage and includes a switch and a capacitor, a DC offset is easily generated, so the discrete time filter requires a supplementary circuit such as a DC offset cancellation circuit in order to cancel the DC offset, and in this case, it is very significant for the supplementary circuit to operate such that it does not affect a main operation of the filter.
FIG. 1 is a first example of a DC offset cancellation circuit according to the related art. In the DC offset cancellation circuit illustrated in FIG. 1, it is noted that both a mixer 12 and a current source 14 include directly connected sampling capacitors Ch1 and Ch2.
The sampling capacitors Ch1 and Ch2 in FIG. 1 are directly provided with an output signal from the mixer 12 and current of the current source 14, and in this case, noise generated from the current source 14 is directly added to the output signal from the mixer 12, degrading the noise performance of the mixer 12.
Also, when switches SWlop and SWlom of the mixer 12 are turned on, a trans-conductance terminal of the mixer 12 and the current source 14 simultaneously operate, making isolation between the two circuits blown up to thereby degrade the performance of the trans-conductance terminal of the mixer 12 and the current source 14.
A pair of transmission switches SWd1 and SWdb1 transfer electric charges charged in the sampling capacitors Cf1 and Cf2 to rotary capacitors Cr1 and Cr2 by transmission signals (D1, D) to form an IIR (Infinite Impulse Response) filter.
Thus, in order to overcome the shortcomings of the noise increase, a DC offset calculation circuit configured by correcting the part after the mixer 12, as shown in FIG. 2, has been proposed.
In the DC offset cancellation circuit illustrated in FIG. 2, a pair of feedback capacitors Cf1 and Cf2 are additionally provided, and the current source 14 is connected to the feedback capacitors Cf1 and Cf2.
The feedback capacitors Cf1 and Cf2 receive current from the current source 14 and primarily store DC offset electric charges, and rotary capacitors Cr21 and Cr22 then transfer them to the sampling capacitors Ch1 and Ch2.
In this case, the rotary capacitors Cr21 and Cr22 are provided so as to perform charge sharing in order to transfer the DC offset electric charges charged in the feedback capacitors Cf1 and Cf2 to the sampling capacitors Ch1 and Ch2, and at this time, an IIR filtering function is conducted in the rotary capacitors Cr21 and Cr22. As a result, noise from the current source 14 is filtered out and only the DC offset electric charges are transferred to the sampling capacitors Ch1 and Ch2.
Also, in the DC offset cancellation circuit illustrated in FIG. 2, the values of the feedback capacitors Cf1 and Cf2 can be arbitrarily determined, irrespective of the sampling capacitors Ch1 and Ch2 and the rotary capacitors Cr21 and Cr22, having the advantage in that the bandwidth of the IIR filter that filters out noise of the current source 14 and a cut-off frequency can be adjusted according to an operator's intent.
In addition, as mentioned above, because the DC offset electric charges are transferred to the sampling capacitors Ch1 and Ch2 through the feedback capacitors Cf1 and Cf2 and the rotary capacitors Cr21 and Cr22, isolation between the trans-conductance stage of the mixer 12 and the current source 14 can be stably guaranteed.
However, in order to obtain DC offset electric charges in the DC offset cancellation circuit of FIG. 2, the current output from the current source 14 implemented mainly as a current type digital-to-analog converter (current DAC) is charged to the feedback capacitors Cf1 and Cf2 during a certain period of time. In this case, in order to minutely adjust the DC offset electric charges, the resolution of the current type digital-to-converter must be increased, a factor that makes the designing thereof complicated and difficult.
In an effort to solve this problem, a method of replacing the current source part in the structure of FIG. 2 with a sigma-delta converter 31 and using two constant voltage sources VDD and GND as shown in FIG. 3 has been proposed.
The DC offset cancellation circuit illustrated in FIG. 3 has the advantage in that DC offset electric charges can be generated at finer intervals and noise characteristics can be further improved owing to noise shaping characteristics of the sigma-delta converter 31.
However, also, in this case, in order to obtain high resolution and sufficient noise shaping characteristics, the sigma-delta converter 31 must receive a clock (CLK) having a very high frequency.
As a result, in order to minutely adjust the DC offset in the related art, the current type digital-to-analog converter having high resolution or the sigma-delta converter using the high frequency clock must be provided, and this makes the designing of the DC offset cancellation circuit complicated and difficult.